Development of a highly accurate calibration system for PLL circuit miniaturization
Hitachi, Ltd. (NYSE:HIT / TSE: 6501), in cooperation with Elpida Memory, Inc. (President and CEO: Mr. SAKAMOTO Yukio) announced today that they have developed a new methodology for memory-array design, Concordant Memory Design Using Statistical Integration, which gathers statistics on device parameters from each memory cell on the chip for an accurate distribution of memory-cell characteristics, and applies the results to the quantitative evaluation of the memory array.